Stanford and USC researchers have developed software that can predict the best designs for fabricating logic gates from disorganized carbon nanotubes.

To prevent electrical malfunctions, the algorithm uses a combination of the mathematics of complicated networks and Boolean algebra to define various regions on a batch of nanotubes. Depending on the desired function of the circuit, a design is proposed that lays out legal and illegal regions for the gates to exist. When nanotubes cross the boundary into a particular region, explains Mitra, they are chemically etched away so that they won’t conduct an erroneous current to another transistor. The researchers have generalized the approach so that it works not just for NAND gates, but for any arbitrary logic gate as well.