Building block of a programmable neuromorphic substrate: a digital neurosynaptic core

June 22, 2012

Left: neurosynaptic core measures 2mmx3mm, consisting of axons (rows), dendrites (columns), synapses (row–column junctions), and neurons that receive inputs from dendrites. Right: test board that interfaces with the chip via a USB 2.0 link. (Credit: J. V. Arthur et al./International Joint Conference on Neural Networks)

The Cornell – IBM SyNAPSE team has fabricated a key building block of a modular neuromorphic architecture: a neurosynaptic core, IBM Almaden scientist Dr. Dharmendra S Modha’s Cognitive Computing Blog reports.

The core incorporates central elements from neuroscience, including 256 leaky integrate-and-fire neurons, 1024 axons, and 256x1024 synapses using an SRAM crossbar memory. It fits in a 4.2mm square area, using a 45nm SOI process.

A design prototype of the core was announced in August 2011, part of SyNAPSE, a DARPA program that aims to develop electronic neuromorphic (neuron-like) machine technology similar to the mammalian brain. Such artificial brains would be used in robots whose intelligence matches that of rats, cats, and ultimately even humans.

“One of the main obstacles holding back the widespread utility of low-power neuromorphic chips is the lack of a consistent software-hardware neural programming model, where neuron parameters and connections can be learned off-line to perform a task in software with a guarantee that the same task will run on power-efficient hardware,” the team said in an open-access paper.

The core replaces supercomputers and commodity chips (DSP, GPU, FPGA), both of which require high power consumption, the authors say. The compact design is also compatible with mobile devices. It consumes just 45pJ (picojoule) per spike.

“This is a flexible brain-like architecture capable of a wide array of real-time applications, and designed for the ultra-low power consumption and compact size of biological neural systems,” explained Modha.

First aplication of neurosynaptic core: steering a simulated robot around a virtual racetrack -- a physics-based emulation of the real-life MobileRobots Pioneer 3-AT (P3AT), a four-wheel-drive robotic platform with a vision sensor (credit: J. V. Arthur et al./International Joint Conference on Neural Networks)

“The core is fully configurable in terms of neuron parameters, axon types, and synapse states and its fully digital implementation achieves one-to-one correspondence with software simulation models. One-to-one correspondence allows us to introduce an abstract neural programming model for our chip, a contract guaranteeing that any application developed in software functions identically in hardware.”

This allows researchers to rapidly test and map applications for control, machine vision, and classification.

To demonstrate, they developed four test cases: a robot driving in a virtual environment, the classic game of pong, visual digit recognition, and an autoassociative memory.

(a) Simulation of the classic Pong video game. Schema of the underlying architecture of the neural network. Excitatory connections are red, inhibitory connections are blue, and excitatory self-connections are black. Areas of projecting or projected excitatory/inhibitory connections are red/blue circled. (b) Left: representation of the Pong game area and right: example traces of active neurons left by the ball trajectory (white squares), and the motor neuron corresponding to the position of the paddle center (upper grid in red). The red arrow indicates the paddle’s initial and final position. (c) Three examples of the neural player after training. (Credit: J. V. Arthur et al./International Joint Conference on Neural Networks)