A high-k dielectric (gate insulation) process for CMOS transistors promises to eliminate the gate-leakage problem at advanced semiconductor nodes down to 10 nanometers, extending the International Semiconductor Roadmap.

Overheating due to excessive gate leakage is the number one hurdle to reaching advanced semiconductor nodes below 45 nanometer. Now, a process with 1 million times less gate leakage could enable rapid migration to advanced nodes, according to Clemson University researchers.