Nanoscale patterning of silicon substrates with regular, repeatable, atomically perfect application-specific templates could enable manufacturable nanoscale chips within the decade, according to scientists at the University of Wisconsin’s Materials Research Science and Engineering Center (Madison).

The technique can achieve dimensions of tens of nanometers and could someday result in a computer with 4,000 Gbytes of memory. The team used block co-polymers that “self-assemble like snowflakes,” according to their report, enabling nanoscale patterns to form only in designated areas on a chip in a manner similar to conventional lithography.

Future silicon substrates could host arrays of identical molecular-size components and ake advantage of conducting polymers to someday interconnect those components with nanoscale wiring.