Stanford engineers have build 3D “high-rise” chips that could leapfrog the performance of the single-story logic and memory chips on today’s circuit cards, which are subject to frequent traffic jams between logic and memory.

The Stanford approach would attempt to end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip. Many thousands of nanoscale electronic “elevators” would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.

The work is led by Subhasish Mitra, a Stanford associate professor of electrical engineering and of computer science, and H.-S. Philip Wong, the Williard R. and Inez Kerr Bell Professor in Stanford’s School of Engineering. They describe their new high-rise chip architecture in a paper being presented at the IEEE International Electron Devices Meeting Dec. 15–17.

The researchers’ innovation leverages three breakthroughs: a new technology for creating transistors using nanotubes, a new type of computer memory that lends itself to multi-story fabrication, and a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.

“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.” Wong said the prototype chip unveiled at IEDM shows how to put logic and memory together into three-dimensional structures that can be mass-produced.

“Paradigm shift is an overused concept, but here it is appropriate,” Wong said. “With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand.”

Overcoming silicon heat

Researchers have been trying to solve a major problem with chip-generated heat by creating carbon nanotubes (CNT)  transistors. Mitra and Wong are presenting a second paper at the conference showing how their team made some of the highest performance CNT transistors ever built.

Until now the standard process used to grow CNTs did not create sufficient density. The Stanford engineers solved this problem  an ingenious technique. They started by growing CNTs the standard way, on round quartz wafers. Then they created a metal film that acts like a tape. Using this adhesive process, they lifted an entire crop of CNTs off the quartz growth medium and placed it onto a silicon wafer that would become the foundation of their high-rise chip.

They repeated this process 13 times, achieving some of the highest density, highest performance CNTs ever made. Moreover, the Stanford team showed that they could perform this technique on more than one layer of logic as they created their high-rise chip.

RRAM memory

Wong is a world leader in a new memory technology called “resistive random access memory” (RRAM) which he unveiled at last year’s IEDM conference.

Unlike today’s memory chips, this new storage technology is not based on silicon, but titanium nitride, hafnium oxide and platinum. This formed a metal/oxide/metal sandwich. Applying electricity to this three-metal sandwich one way causes it to resist the flow of electricity. Reversing the polarity causes the structure to conduct electricity again.

The change from resistive to conductive states is how this new memory technology creates digital zeroes and ones.

RRAM uses less energy than current memory, leading to prolonged battery life in mobile devices. Inventing this new memory technology was also the key to creating the high-rise chip because RRAM can be made at much lower temperatures than silicon memory.

Interconnected layers

Max Shulaker and Tony Wu, Stanford graduate students in electrical engineering, created the techniques behind the four-story high-rise chip unveiled at the conference.

The low-heat process for making RRAM and CNTs enabled them to fabricate each layer of memory directly atop each layer of CNT logic. While making each memory layer, they were able to drill thousands of interconnections into the logic layer below. This multiplicity of connections is what enables the high-rise chip to avoid the traffic jams on conventional circuit cards.

There is no way to tightly interconnect layers using today’s conventional silicon-based logic and memory. That’s because it takes so much heat to build a layer of silicon memory — about 1,000 degrees Celsius — that any attempt to do so would melt the logic below.

Previous efforts to stack silicon chips could save space but not avoid the digital traffic jams. That’s because each layer would have to be built separately and connected by wires — which would still be prone to traffic jams, unlike the nanoscale elevators in the Stanford design.